1/10 october 2002 n 3.6v tolerant inputs and outputs n high speed : t pd = 4.6 ns (max.) at v cc =3.0to3.6v t pd = 5.4 ns (max.) at v cc =2.3to2.7v t pd = 6.5 ns (max.) at v cc =1.65v n power down protection on inputs and outputs n symmetrical output impedance: |i oh |=i ol = 24ma (min) at v cc =3.0v |i oh |=i ol = 18ma (min) at v cc =2.3v |i oh |=i ol =4ma(min)atv cc = 1.65v n bus hold provided on data inputs n 26 w serie resistors in outputs n operating voltage range: v cc (opr) = 1.65v to 3.6v n pin and function compatible with 74 series 16374 n latch-up performance exceeds 300ma (jesd 17) n esd performance: hbm > 2000v (mil std 883 method 3015); mm > 200v description the 74alvch162374 is a low voltage cmos 16 bit d-type latch with 3 state outputs non inverting fabricated with sub-micron silicon gate and five-layer metal wiring c 2 mos technology. it is ideal for low power and very high speed 1.65 to 3.6v applications; it can be interfaced to 3.6v signal environment for both inputs and outputs. these flip-flops are controlled by two clock inputs (nck) and two output enable inputs (noe ). onthepositivetransitionofthe(nck),thenq outputs will be set to the logic state that were setup at the nd inputs. while the (noe ) input is low, the outputs (nq) will be in a normal state (high or low logic level) and while high level the outputs will be in a high impedance state. any output control does not affect the internal operation of flip flops; that is, the old data can be retained or the new data can be entered even while the outputs are off.the device circuits is including 26 w series resistance in the outputs. these resistors permit to reduce line noise in high speed applications. all inputs and outputs are equipped with protection circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. 74alvch162374 low voltage cmos 16-bit d-type flip-flop (3-state) with 3.6v tolerant inputs and outputs this is preliminary information on a new product now in development are or undergoing evaluation. details subject to change without notice. order codes package tube t & r tssop 74alvch162374t tssop preliminary data pin connection
74alvch162374 2/10 input and output equivalent circuit pin description truth table x : dont care z : high impedance iec logic symbols pin no symbol name and function 1 1oe 3 state output enable input (active low) 2, 3, 5, 6, 8, 9, 11, 12 1q0 to 1q7 3-state outputs 13, 14, 16, 17, 19, 20, 22, 23 2q0 to 2q7 3-state outputs 24 2oe 3 state output enable input (active low) 25 2ck clock input 36, 35, 33, 32, 30, 29, 27, 26 2d0 to 2d7 data inputs 47, 46, 44, 43, 41, 40, 38, 37 1d0 to 1d7 data inputs 48 1ck clock input 4, 10, 15, 21, 28, 34, 39, 45 gnd ground (0v) 7, 18, 31, 42 v cc positive supply voltage inputs output oe ck d q hxx z l x no change lll lhh
74alvch162374 3/10 logic diagram absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied 1) i o absolute maximum rating must be observed 2) v o v cc recommended operating conditions 1) v in from 0.8v to 2v at v cc =3.0v symbol parameter value unit v cc supply voltage -0.5 to +4.6 v v i dc input voltage -0.5 to +4.6 v v o dc output voltage (off state) -0.5 to +4.6 v v o dc output voltage (high or low state) (note 1) -0.5 to v cc + 0.5 v i ik dc input diode current -50 ma i ok dc output diode current (note 2) -50 ma i o dc output current 50 ma i cc or i gnd dc v cc or ground current per supply pin 100 ma p d power dissipation 400 mw t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage 1.65 to 3.6 v v i input voltage -0.3 to 3.6 v v o output voltage (off state) 0 to 3.6 v v o output voltage (high or low state) 0 to v cc v i oh ,i ol high or low level output current (v cc = 3.0 to 3.6v) 12 ma i oh ,i ol high or low level output current (v cc = 2.3 to 2.7v) 6ma i oh ,i ol high or low level output current (v cc = 1.65v) 2ma t op operating temperature -55 to 125 c dt/dv input rise and fall time (note 1) 0 to 10 ns/v
74alvch162374 4/10 dc specifications symbol parameter test condition value unit v cc (v) -40 to 85 c -55 to 125 c min. max. min. max. v ih high level input voltage 1.65 to 1.95 0.65 vcc 0.65 vcc v 2.3 to 2.7 1.7 1.7 2.7 to 3.6 2.0 2.0 v il low level input voltage 1.65 to 1.95 0.35 vcc 0.35 vcc 2.3 to 2.7 0.7 0.7 2.7 to 3.6 0.8 0.8 v oh high level output voltage 1.65 to 3.6 i o =-100 m av cc -0.2 v cc -0.2 v 1.65 i o =-2 ma 1.2 1.2 2.3 i o =-4 ma 2.0 2.0 2.3 i o =-6 ma 1.7 1.7 2.7 i o =-8 ma 2.2 2.2 3.0 i o =-6 ma 2.4 2.4 3.0 i o =-12 ma 2.0 2.0 v ol low level output voltage 1.65 to 3.6 i o =100 m a 0.2 0.2 v 1.65 i o =2 ma 0.45 0.45 2.3 i o =4 ma 0.4 0.4 2.3 i o =6 ma 0.55 0.55 2.7 i o =8 ma 0.6 0.6 3.0 i o =12 ma 0.8 0.8 i i input leakage current 3.6 v i = 0 or 3.6v 5 5 m a i ihold bus hold input leakage current 1.65 v i =0.58 v +25 +25 m a 1.65 v i =1.07 v -25 -25 2.3 v i =0.7 v +45 +45 2.3 v i =1.7 v -45 -45 3.0 v i =0.8 v +75 +75 3.0 v i =2 v -75 -75 3.6 v i = 0 to 3.6 v 500 500 i off power off leakage current 0v i or v o = 3.6v 10 20 m a i oz high impedance output leakage current 3.6 v i =v ih or v il v o = 0 to v cc 5 10 m a i cc quiescent supply current 3.6 v i =v cc or gnd i o =0 20 40 m a d i cc i cc incr. per input 3.0 to 3.6 v ih =v cc - 0.6v 500 750 m a
74alvch162374 5/10 ac electrical characteristics symbol parameter test condition value unit v cc (v) c l (pf) r l ( w ) t s = t r (ns) -40 to 85 c -55 to 125 c min. max. min. max. t plh t phl propagation delay time ck to qn 1.65 to 1.95 30 1000 2.0 1 6.5 1 6.5 ns 2.3 to 2.7 30 500 2.0 1 5.4 1 5.4 2.7 50 500 2.5 1 5.4 1 5.4 3.0 to 3.6 50 500 2.5 1 4.6 1 4.6 t pzl t pzh output enable time 1.65 to 1.95 30 1000 2.0 1 8.0 1 8.0 ns 2.3 to 2.7 30 500 2.0 1 6.5 1 6.5 2.7 50 500 2.5 1 6.4 1 6.4 3.0 to 3.6 50 500 2.5 1 5.2 1 5.2 t plz t phz output disable time 1.65 to 1.95 30 1000 2.0 1 6.8 1 6.8 ns 2.3 to 2.7 30 500 2.0 1 5.6 1 5.6 2.7 50 500 2.5 1 5 1 4.5 3.0 to 3.6 50 500 2.5 1 4.5 1 4.5 t s setup time, high or low level dn to ck 1.65 to 1.95 30 1000 2.0 2.1 2.1 ns 2.3 to 2.7 30 500 2.0 2.1 2.1 2.7 50 500 2.5 2.2 2.2 3.0 to 3.6 50 500 2.5 1.9 1.9 t h hold time high or low level dn to ck 1.65 to 1.95 30 1000 2.0 0.8 0.8 ns 2.3 to 2.7 30 500 2.0 0.6 0.6 2.7 50 500 2.5 0.5 0.5 3.0 to 3.6 50 500 2.5 0.5 0.5 t w ck pulse width, high 1.65 to 1.95 30 1000 2.0 4 4 ns 2.3 to 2.7 30 500 2.0 3.3 3.3 2.7 50 500 2.5 3.3 3.3 3.0 to 3.6 50 500 2.5 3.3 3.3 f max maximum clock pulse frequency 1.65 to 1.95 30 1000 2.0 120 120 mhz 2.3 to 2.7 30 500 2.0 150 150 2.7 50 500 2.5 200 200 3.0 to 3.6 50 500 2.5 300 300
74alvch162374 6/10 capacitive characteristics 1) c pd is defined as the value of the ics internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) =c pd xv cc xf in +i cc /16 (per circuit) test circuit r t =z out of pulse generator (typically 50 w ) test circuit and waveform symbol value symbol parameter test condition value unit v cc (v) t a =25c min. typ. max. c in input capacitance control inputs 3.3 v in =v cc or gnd 3pf c in input capacitance data inputs 3.3 v in =v cc or gnd 6pf c out output capacitance 3.3 v in = 0 to v cc 7pf c pd power dissipation capacitance output enabled (note 1) 3.3 f in = 10mhz c l =50pf v in = 0 or v cc 19 pf 2.5 16 c pd power dissipation capacitance output disabled (note 1) 3.3 5 2.5 4 test switch t plh ,t phl open t pzl ,t plz (v cc = 3.0 to 3.6v) 6v t pzl ,t plz (v cc = 2.3 to 2.7v) 2v cc t pzh ,t phz gnd symbol v cc 3.0 to 3.6v 2.7v 2.3 to 2.7v 1.65 to 1.95v v ih 2.7v 2.7v v cc v cc v m 1.5v 1.5v v cc /2 v cc /2 v x v ol +0.3v v ol +0.3v v ol +0.15v v ol +0.15v v y v oh -0.3v v oh -0.3v v oh -0.15v v oh -0.15v c l 50pf 50pf 30pf 30pf r l =r 1 500 w 500 w 500 w 1000 w t r =t r <2.5ns <2.5ns <2.0ns <2.0ns
74alvch162374 7/10 waveform 1 : propagation delays, ck minimum pulse width, dn to ck setup and hold times, ck maximum frequency (f=1mhz; 50% duty cycle) waveform 2: output enable and disable time (f=1mhz; 50% duty cycle)
74alvch162374 8/10 waveform 3 : ck minimum pulse width (f=1mhz; 50% duty cycle)
74alvch162374 9/10 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.006 a2 0.9 0.035 b 0.17 0.27 0.0067 0.011 c 0.09 0.20 0.0035 0.0079 d 12.4 12.6 0.408 0.496 e 8.1 bsc 0.318 bsc e1 6.0 6.2 0.236 0.244 e 0.5 bsc 0.0197 bsc k0? 8?0? 8? l 0.50 0.75 0.020 0.030 tssop48 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 7065588c
74alvch162374 10/10 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no res ponsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devi ces or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com
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